Field of the Invention
The present disclosure relates to a method of aligning and bonding a first substrate and a second substrate for the fabrication of a semiconductor device. The disclosure also relates to semiconductor device aligned and bonded according to the method.
Description of the Related Technology
In one aspect, the present disclosure applies to the field of 3D thin die packaging or multiple thin IC (devices) packaging in the semiconductor industry. The assembly of semiconductor devices in three dimensions (3D) is an enabler for advanced scaling and integration of components, especially in case of heterogeneous components, for instance logic, memory and transducers, etc.
Often multiple metal “pads” or “bumps” need to be electrically joined to opposing parallel surfaces (metal to metal joining). The currently applied processes for the assembly of semiconductor devices typically involve wire bonding and/or welding and/or gluing the devices.
In a typical wire bonding process wires are bonded to a number of stacked substrates in order to provide electrical connectivity. The wire bonding process is time consuming, relatively complex, and enables only a limited wiring density between the dies. Furthermore, the wire bonding process results in a structure having an essentially “pyramidal” shape, which reduces the useful area of the dies.
Alternatives for the wire bonding processes may be welding and/or gluing processes. Examples are thermo-compression bonding of metals and welding. These assembly processes typically occur under high forces and/or at high temperatures, for instance ranging from 150° C. up to 350° C. These temperatures may be too high for devices in certain applications, such as advanced memory chips and MEMS devices. For some applications the metal-to-metal joining needs to be done at low temperature, much below the melting temperature of the metals, without the use of intermediate soldering metals. Also low pressure is needed for some applications.
An example of such an application is the field of three dimensional (3D) integration. 3D ICs provide a way of integration that would enable high performance, compact System-on-chips (SoCs). Fabrication of 3D ICs 15 involves stacking of a first chip 10 on a second chip 11 such that FEOL (front end of line) and BEOL (back end of line) structures on both (or more) these chips 10, 11 are connected using Through Silicon Vias (TSV) 12 as shown in FIG. 1. Through Silicon Vias (TSV) 12 form an interconnect component connecting the different dies 10, 11 of the 3D IC.
Traditional thermo-compression bonding consists of mating a metal bump structure 20 to a flat metal surface 21 by applying a perpendicular force F on the joint that causes the bump structure 20 to deform. As a result of the small plastic flow during deformation, an intimate metal-metal contact is obtained at the joining interface. Adsorbed molecules and possible surface oxides are removed by tangential deformations caused by shear forces at the contact surface. This is illustrated in FIG. 2, where the left hand side illustrates the situation before thermo-compression, and the right hand side illustrates the situation after thermo-compression.
Tanaka et al. describe in “Low-cost Through-hole Electrode Interconnection for 3D-SiP Using Room-temperature Bonding”, IEEE, Electronic Components and Technology Conference 2006, p. 814-818, a method for making through-hole electrode interconnections by a mechanical caulking operation. Multiple through-hole electrodes are formed on the backside of a lower chip. Gold stud bumps on the upper chips are pressed into the through-hole electrodes on the lower chips by applying a compressive force, which causes the gold bump to plastically deform. A contact force is generated at the interface between the bumps and the electrodes on the sidewall of the through-holes. The bumps have a degrading dimension in a direction from the substrate to the tip of the bump.
In US20060170112, a method of joining parts using large stud bumps (made by a Au-wire bonder) on one surface and gold-metalized pits on the other surface is described. The joining is performed by pushing and deforming the Au stud bumps in the mating holes of the bottom substrate. During this action, the plastic flow of the metal bump allows for a tight filling, “caulking”, of the bottom hole, realizing an intimate metal-metal contact between the two parts. This method requires large Au bumps, large deformations and deep holes in the mating substrate. These holes are characterized by a diameter smaller than the Au bumps, having vertical side-wall profiles.